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| a FEATURES Bandwidth - 110 MHz Slew Rate - 3000 V/ s Low Offset Voltage - <1 mV Very Low Noise - < 4 nV/Hz Low Supply Current - 8.5 mA Mux Wide Supply Range - 5 V to 15 V Drives Capacitive Loads Pin Compatible with BUF03 APPLICATIONS Instrumentation Buffer RF Buffer Line Driver High Speed Current Source Op Amp Output Current Booster High Performance Audio High Speed AD/DA GENERAL DESCRIPTION 8-Lead Narrow-Body SO (S Suffix) 1 Closed-Loop High Speed Buffer BUF04* FUNCTIONAL BLOCK DIAGRAMS Plastic DIP 8-Lead and Cerdip (P, Z Suffix) NULL 1 8 7 6 5 NC = NO CONNECT NULL V+ OUT NC BUF04 BUF04 Top View NC 2 IN 3 V- 4 The BUF04 is a wideband, closed-loop buffer that combines state of the art dynamic performance with excellent dc performance. This combination enables designers to maximize system performance without any speed versus dc accuracy compromises. Built on a high speed Complementary Bipolar (CB) process for better power performance ratio, the BUF04 consumes less than 8.5 mA operating from 5 V or 15 V supplies. With a 2000 V/s min slew rate, and 100 MHz gain bandwidth product, the BUF04 is ideally suited for use in high speed applications where low power dissipation is critical. Full 10 V output swing over the extended temperature range along with outstanding ac performance and high loop gain accuracy makes the device useful in high speed data acquisition systems. High slew rate and very low noise and THD, coupled with wide input and output dynamic range, make the BUF04 an excellent choice for video and high performance audio circuits. The BUF04's inherent ability to drive capacitive loads over a wide voltage and temperature range makes it extremely useful for a wide variety of applications in military, industrial, and commercial equipment. The BUF04 is specified over the extended industrial (-40C to +85C) and military (-55C to +125C) temperature range. BUF04s are available in plastic and ceramic DIP plus SO-8 surface mount packages. Contact your local sales office for MIL-STD-883 data sheet and availability. *Patent pending. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 BUF04-SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = S 15.0 V, TA = +25 C unless otherwise noted) Min Typ Max Units Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Voltage Range Offset Voltage Drift Offset Null Range OUTPUT CHARACTERISTICS Output Voltage Swing VOS IB VCM VOS/T -40C TA +85C VCM = 0 -40C TA +85C 0.3 1.3 0.7 2.2 13 30 25 10.5 10 13 13 50 11.1 11 13.5 13.15 65 80 1 4 5 10 mV mV A A V V/C mV V V V V mA mA V/V V/V % % dB dB mA mA V/s MHz MHz MHz ns Degrees Degrees % % pF nV/Hz pA/Hz VO RL = 150 , -40C TA +85C RL = 2 k, -40C TA +85C Note 2 RL = 2 k -40C TA +85C RL = 1 k, VO = 10 V RL = 150 k VS = 4.5 V to 18 V -40C TA +85C VO = 0 V, RL = -40C TA +85C RL = 2 k, CL = 70 pF -3 dB, CL = 20 pF, RL = -3 dB, CL = 20 pF, RL = 1 k -3 dB, CL = 20 pF, RL = 150 VIN = 10 V Step to 0.1% f = 3.58 MHz, RL = 150 f = 4.43 MHz, RL = 150 f = 3.58 MHz, RL = 150 f = 4.43 MHz, RL = 150 Output Current - Continuous Peak Output Current TRANSFER CHARACTERISTICS Gain Gain Linearity POWER SUPPLY Power Supply Rejection Ratio Supply Current DYNAMIC PERFORMANCE Slew Rate Bandwidth Bandwidth Bandwidth Settling Time Differential Phase Differential Gain Input Capacitance NOISE PERFORMANCE Voltage Noise Density Current Noise Density IOUT IOUTP AVCL NL 0.995 0.995 0.9985 1.005 0.9980 1.005 0.005 0.008 93 93 6.9 6.9 3000 110 110 110 60 0.02 0.03 0.014 0.008 3 4 2 PSRR ISY 76 76 8.5 8.5 SR BW BW BW 2000 en in f = 1 kHz f = 1 kHz NOTE 1 Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 C with an LTPD of 1.3. Specifications subject to change without notice. -2- REV. 0 BUF04 ELECTRICAL CHARACTERISTICS (@ V = S 5.0 V, TA = +25 C unless otherwise noted) Min Typ Max Units Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Voltage Range Offset Voltage Drift Offset Null Range OUTPUT CHARACTERISTICS Output Voltage Swing VOS IB VCM VOS/T -40C TA +85C VCM = 0 V -40C TA +85C 0.8 1.0 0.15 1.6 3.0 30 25 3.0 2.75 3.0 3.0 40 2.0 4 5 10 mV mV A A V V/C mV V V V V mA mA V/V V/V % dB dB mA mA V/s MHz MHz MHz Degrees Degrees % % nV/Hz pA/Hz VO RL = 150 , -40C TA +85C RL = 2 k, -40C TA +85C Note 2 RL = 2 k, -40C TA +85C RL = 1 k VS = 4.5 V to 18 V -40C TA +85C VO = 0 V, RL = -40C TA +85C RL = 2 k, CL = 70 pF -3 dB, CL = 20 pF, RL = -3 dB, CL = 20 pF, RL = 1 k -3 dB, CL = 20 pF, RL = 150 f = 3.58 MHz, RL = 150 f = 4.43 MHz, RL = 150 f = 3.58 MHz, RL = 150 f = 4.43 MHz, RL = 150 f = 1 kHz f = 1 kHz 3.00 3.6 3.35 75 0.9977 1.005 1.005 0.005 93 93 6.60 6.70 2000 100 100 100 0.13 0.15 0.04 0.06 4 2 Output Current - Continuous Peak Output Current TRANSFER CHARACTERISTICS Gain Gain Linearity POWER SUPPLY Power Supply Rejection Ratio Supply Current DYNAMIC PERFORMANCE Slew Rate Bandwidth Bandwidth Bandwidth Differential Phase Differential Gain NOISE PERFORMANCE Voltage Noise Density Current Noise Density IOUT IOUTP AVCL NL PSRR ISY 0.995 0.995 76 76 8 8 SR BW BW BW en in NOTE 1 Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 C, with an LTPD of 1.3. Specifications subject to change without notice. REV. 0 -3- BUF04 WAFER TEST LIMITS (@ V = S 15.0 V, TA = +25 C unless otherwise noted) Symbol Conditions Limit Units Parameter Offset Voltage Input Bias Current Power Supply Rejection Ratio Output Voltage Range Supply Current Gain VOS VOS IB PSRR VO ISY AVCL VS = 15 V VS = 5 V VCM = 0 V V = 4.5 V to 18 V RL = 150 VO = 0 V, RL = 2 k VO = 10 V, RL = 2 k 1 2 5 76 10.5 8.5 1 0.005 mV max mV max A max dB V min mA max V/V NOTE Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. ABSOLUTE MAXIMUM RATINGS 1 DICE CHARACTERISTICS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Maximum Power Dissipation . . . . . . . . . . . . . . . See Figure 16 Storage Temperature Range Z Package . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +175C P, S Package . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Operating Temperature Range BUF04Z . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C BUF04S, P . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Junction Temperature Range Z Package . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C P, S Package . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C Package Type JA2 JC Units 8-Pin Cerdip (Z) 8-Pin Plastic DIP (P) 8-Pin SOIC (S) 148 103 158 16 43 43 C/W C/W C/W BUF04 Die Size 0.075 x 0.064 inch, 5,280 Sq. Mils Substrate (Die Backside) Is Connected to V+ Transistor Count 45. NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 JA is specified for the worst case conditions, i.e., JA is specified for device in socket for cerdip, P-DIP, and LCC packages; JA is specified for device soldered in circuit board for SOIC package. ORDERING GUIDE Temperature Range Package Description Package Option Model BUF04AZ/883 BUF04GP BUF04GS BUF04GBC -55C to +125C -40C to +85C -40C to +85C +25C Cerdip Plastic DIP SO DICE Q-8 N-8 SO-8 DICE -4- REV. 0 Typical Performance Characteristics-BUF04 150 VS = 15V 315 PLASTIC DIPS TA = +25C 200 VS = 15V 315 CERDIPS TA = +25C 120 160 90 120 UNITS UNITS 60 80 30 40 0 -0.1 0.0 0.1 0.2 0.3 OFFSET - mV 0.4 0.5 0.6 0 -0.15 -0.1 -0.5 0 0.5 0.1 0.15 0.2 OFFSET - mV Figure 1. Input Offset Voltage (VOS) Distribution @ 15 V, P-DIP 125 VS = 5V 315 PLASTIC DIPS TA = +25C Figure 4. Input Offset Voltage (VOS) Distribution @ 15 V, Cerdip 125 VS = 5V 315 CERDIPS TA = +25C 100 100 75 75 UNITS UNITS 50 50 25 25 0 0 0.2 0.4 0.6 0.8 OFFSET - mV 1.0 1.2 1.4 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OFFSET - mV Figure 2. Input Offset Voltage (VOS) Distribution @ 5 V, P-DIP 2.0 1.0 5V 0 15V Figure 5. Input Offset Voltage (VOS) Distribution @ 5 V, Cerdip 0 VS = 5V -1.0 INPUT BIAS CURRENT - A VS = 15V -2.0 OFFSET - mV -1.0 -2.0 -3.0 -4.0 -5.0 -6.0 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE - C -3.0 -4.0 -5.0 -6.0 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE - C Figure 3. Input Offset Voltage (VOS) vs. Temperature Figure 6. Input Bias Current vs. Temperature REV. 0 -5- BUF04 8.0 50 45 TA = +25C 7.5 VS = 18V 7.0 VS = 15V 6.5 VS = 5V OUTPUT IMPEDANCE - 40 35 30 25 20 15 10 5 VS = 15V VS = 5V SUPPLY CURRENT - mA 6.0 5.5 -75 0 -50 -25 0 25 50 75 100 125 1k 10k TEMPERATURE - C 100k 1M FREQUENCY - Hz 10M 100M Figure 7. Supply Current vs. Temperature 15 14 13 VS = 15V RL = 2k RL = 1k Figure 10. Output Impedance vs. Frequency 5.0 4.5 4.0 VS = 5V RL = 2k , 1k RL = 150 OUTPUT SWING - Volts OUTPUT SWING - Volts 12 11 RL = 150 3.5 3.0 -11 -12 -13 -14 -15 -75 RL = 150 -3.0 -3.5 -4.0 -4.5 -5.0 -75 RL = 150 RL = 1k RL = 2k -50 -25 25 50 TEMPERATURE - C 0 75 100 125 RL = 2k , 1k -50 -25 25 50 0 TEMPERATURE - C 75 100 125 Figure 8. Output Voltage Swing vs. Temperature @ 15 V 5 Figure 11. Output Voltage Swing vs. Temperature @ 5 V 16 14 4 OUTPUT SWING - Volts 12 10 8 6 4 2 OUTPUT SWING - Volts 3 POSITIVE SWING POSITIVE SWING 2 ABS NEGATIVE SWING ABS NEGATIVE SWING VS = 15V TA = +25C 1 VS = 5V TA = +25C 0 10 100 1k 10k 100k 1M LOAD RESISTANCE - 0 10 100 1k 10k LOAD RESISTANCE - Figure 9. Maximum VOUT Swing vs. Load @ 5 V Figure 12. Maximum VOUT Swing vs. Load @ 15 V -6- REV. 0 BUF04 0.5 1.5 P DIP JA = 103C/W TJ MAX = 150C FREE AIR NO HEAT SINK 0 INPUT BIAS CURRENT - A TA = +25C POWER DISSIPATION - W 1.0 -0.5 CERDIP JA = 148C/W -1.0 SOIC JA = 158C/W 0.5 -1.5 -2.0 -10 0 -8 -6 -4 -2 0 2 4 6 8 10 0 25 50 75 85 100 125 COMMON MODE VOLTAGE - Volts TEMPERATURE - C Figure 13. Bias Current vs. Input Voltage Figure 16. Maximum Power Dissipation vs. Ambient Temperature 100 100 90 POWER SUPPLY REJECTION - dB 80 70 60 50 40 30 20 10 0 1k 10k 100k 1M 10M 100M FREQUENCY - Hz +PSRR - PSRR INPUT NOISE VOLTAGE SPECTRAL DENSITY - nV/ Hz TA = +25C VS = 5, 15V 10 0 1 10 100 1k 10k 100k 1M FREQUENCY - Hz Figure 14. Power Supply Rejection vs. Frequency 6000 VS = 15V 5000 +EDGE Figure 17. Input Noise Voltage vs. Frequency 6000 VS = 15V SWING = 10V TA = +25C POSITIVE SLEW RATE 5000 SLEW RATE - V/s SLEW RATE - V/s 4000 4000 3000 -EDGE 2000 3000 NEGATIVE SLEW RATE 2000 1000 1000 0 -75 0 -50 -25 0 25 50 75 100 125 TEMPERATURE - C 0 50 100 150 200 250 CAPACITIVE LOAD - pF Figure 15. Slew Rate vs. Temperature Figure 18. Slew Rate vs. Capacitive Loads REV. 0 -7- BUF04 150 TA = +25C VS = 5V -45 150 TA = +25C VS = 15V -45 125 -67.5 125 -67.5 BANDWIDTH - MHz BANDWIDTH - MHz PHASE - Deg PHASE @ RL = 150 -112.5 PHASE @ RL = 2k 75 75 RL = 2k -112.5 50 -135 50 -135 25 BANDWIDTH -157.5 25 PHASE -157.5 0 0 50 100 150 200 CAPACITANCE - pF -180 250 0 0 50 100 150 200 CAPACITANCE - pF -180 250 Figure 19. Bandwidth and Phase vs. Capacitive Loads @ 5 V 140 RL= 2k 130 -55C 150 200 Figure 22. Bandwidth & Phase vs. Capacitive Loads @ 15 V TA = +25C VS = 15V BANDWIDTH - MHz 120 +25C 110 BANDWIDTH - MHz 100 100 +125C 50 90 80 5 10 SUPPLY VOLTAGE -Volts 15 0 100 1k RESISTIVE LOAD - 10k Figure 20. Bandwidth vs. Supply Voltage and Temperature 1.5 VS = 15V VIN = 0.1VRMS FREQUENCY = 10MHz RL = 150 6 Figure 23. Bandwidth vs. Loads 1.5 VS = 15V VIN = 0.1VRMS FREQUENCY = 10MHz RL = 2k GAIN 0.075 PHASE 2 PHASE DEVIATION - Degrees 0.5 0.025 0.5 0 0 0 0 -0.5 GAIN -2 -0.025 PHASE -0.050 -0.5 -1.0 -4 -1.0 -1.5 -10 -6 -8 -6 -4 -2 2 4 0 OUTPUT VOLTAGE - Volts 6 8 10 -0.075 -10 -1.5 -8 -6 -4 2 4 0 OUTPUT VOLTAGE - Volts -2 6 8 10 Figure 21. Gain and Phase Deviation, RL = 150 Figure 24. Gain and Phase Deviation, RL = 2 k -8- REV. 0 PHASE DEVIATION - Degrees 1.0 4 0.050 1.0 GAIN DEVIATION - dB GAIN DEVIATION - dB PHASE - Deg 100 -90 100 BANDWIDTH RL = 150 -90 BUF04 DLY 100 375.0ns 100 INPUT (50mV/DIV) 90 INPUT (2V/DIV) 90 OUTPUT (50mV/DIV) 10 0% OUTPUT (2V/DIV) 10 0% 50mV 50mV 10ns 2V 2V 50ns VS = 15V, RL = 2k, CL = 15pF VS = 15V, RL = 2k, CL = 15pF Figure 25. Small-Signal Transient Response AUDIO PRECISION BUF04 THD+N (%) vs FREQ (Hz) 0.1 07 MAR 93 21:31:53 Figure 26. Large-Signal Transient Response 12 9 VS = 15V TA = +25C RL = 150 CL = 100pF VS= 15V LPF=80kHz A : VIN = 7.75Vrms, RL= 150W A B B : VIN = 7.75Vrms, RL= 600W C : VIN = 0.775Vrms, RL= 150W D : VIN = 0.775Vrms, RL= 600W 6 3 0 -3 A 0.010 GAIN - dB C CL = 50pF CL = 0pF B C 0.001 D D 150 BUF04 -6 CL 10 -9 0.0001 20 T 100 1k 10k 20k -12 10k 100k 1M 10M FREQUENCY - Hz 100M 1000M Figure 27. THD + Noise vs. Amplitude FUNCTIONAL DESCRIPTION Figure 28. Bandwidth vs. Frequency The BUF04 is a closed-loop voltage buffer based on a current feedback architecture. Its high open-loop transimpedance, high output current drive capability, and its low input offset voltage makes it useful in a variety of applications, such as buffering the inputs of sampling and flash A/D converters, audio and video line drivers, active filters, and precision op amp hoosters. A transistor-level equivalent circuit for the BUF04 is illustrated in Figure 29. The input stage consists of a pair of emitter follower transistors, Q1 and Q2, whose outputs drive a second set of transistors, Q3 and Q4. The emitters of Q3 and Q4 are connected together through diodes, D1 and D2, to form a low impedance input for the feedback signal (in current mode) from the output stage. The outputs of Q3 and Q4 are then "mirrored" to Q5 and Q6 which form the gain stage of the BUF04. The signal is taken from the collectors of Q5 and Q6 which drive a "Darlington-connected" output stage made up of transistors Q7-Q10. Three R-C networks (R1-C1, R2-C2, and R3-C3) form feed-forward paths which bypass certain sections of the BUF04 for improved high frequency performance and capacitive load drive capability. Since the signal conveyed internally in the BUF04 is a current, the frequency response and slew rate of the BUF04 are insensitive to supply voltage variations. Q11 Q13 Q5 Q7 Q3 C1 Q9 D1 Q2 VIN Q1 D2 RFB 100 C3 R3 20 VOUT R2 20 Q10 Q4 C2 Q8 Q6 Q14 Q12 Figure 29. Transistor-Level Equivalent Circuit An interesting feature of the BUF04 architecture is the use of "slew-enhancement" transistors, Q11-Q14. Under normal small signal (VIN < 2 Vbes) conditions, these transistors are normally "OFF." In large signals, high speed transient applications where the input signal is > 2 Vbes, these transistors turn on and literally "brute-force" the output to follow the input. When the input signal drops below 2 Vbes, the transistors return to their normally "OFF" state. REV. 0 -9- BUF04 A two-terminal equivalent circuit of the BUF04 is shown in Figure 30 where the transistor-level equivalent circuit is reduced to its essential elements. The input stage develops a signal current, IIN, that is replicated by an internal current conveyor so as to flow through Rt, the transimpedance of the BUF04. The voltage developed across Rt is buffered by a unity-gain output voltage follower. With an open-loop Rt of 400 k and an RIN of 30 , the voltage gain of the BUF04, given by the ratio Rt/RIN is approximately 13,000--accurate to approximately 13.5 bits. The BUF04's open-loop ac transimpedance response is determined by the open-loop pole formed by Rt and Ct. Since Ct is typically 8 pF, the open-loop pole occurs at approximately 50 kHz. To minimize the effects of high-frequency coupling, circuits must be built with short interconnect leads, and large ground planes should he used whenever possible to provide a low resistance, low-inductance circuit path. Sockets should be avoided because the increased interlead capacitance can degrade bandwidth and stability. If sockets are necessary, individual pin sockets (oftentimes called "cage jacks," AMP Part No. 5-330808-3 or 5-330808-6) should be used. They contribute far less stray reactance than molded socket assemblies. Offset Voltage Nulling VIN X1 IIN RIN RFB RIN = 30 Rt = 400 k Ct = 8pF RFB = 100 Rt IIN Ct XI VOUT Although the offset voltage of the BUF04 is very low (1 mV, maximum) for such a high speed buffer, the circuit shown in Figure 32 can be used if additional offset voltage nulling is required. A potentiometer ranging from 1 k to 10 k can be used for VOS nulling; with a 10 k potentiometer, the trim range is 30 mV. V+ TRIM RANGE 30mV 1 VIN 3 10F 0.1F 10k 8 7 6 0.1F 10F BUF04 4 VOUT Figure 30. Current-Feedback Functional Equivalent Circuit of the BUF04 Grounding and Bypassing Considerations V- To take full advantage of the BUF04's very wide bandwidth, high slew rates, and dynamic range capabilities requires due diligence with regard to supply bypassing. In high speed circuits, the supply bypassing network must provide a very low impedance return path for currents flowing to and from the load network. As with any high speed application, multiple bypassing is always recommended. A 10 F tantalum electrolytic in parallel with a 0.1 F ceramic capacitor is sufficient for most applications. For those high speed applications where output load currents approach 50 mA, small valued resistors (1.1 to 4.7 ) in series with the tantalum capacitors may improve circuit transient response by damping out the capacitor's selfinductance. Figure 31 illustrates bypassing recommendations. V+ 10F R1 0.1F KELVIN RETURN FOR LOAD CURRENT 6 RL 0.1F VOUT Figure 32. Optional Offset Voltage Nulling Scheme APPLICATIONS Output Short-Circuit Protection To optimize the transient response and output voltage swing of the BUF04, internal output short-circuit current limiting was omitted. Although the BUF04 can provide continuous output currents of 50 mA without protection, direct connection of the BUF04's output to ground or to the supplies will destroy the device. An active current limit technique, illustrated in Figure 33, provides the necessary short-circuit protection while retaining full dc output voltage swing to the load. +15V 10F RSC1 10 2N2905 2N2905 0.1F 7 VIN 3 BUF04 4 6 0.1F 6.2k SET ISC +(ISC-) <60mA, CONTINUOUS 0.6V RSC1 (RSC2) = ISC + (ISC-) VOUT 0.01F 7 VIN RS 3 BUF04 4 10F R2 KELVIN RETURN FOR LOAD CURRENT 2N2219 2N2219 RSC2 10 10F V- NOTE USE SHORT LEAD LENGTHS (<5mm) Figure 31. Recommended Power-Supply Bypassing -15V Figure 33. Short-Circuit Current Limiting Using Current Sources -10- REV. 0 BUF04 Output Current Transient Recovery Settling characteristics of high speed buffers also include the buffer's ability to recover, i.e., settle, from a transient output current load condition. When driving the input of an A/D converter, especially the successive-approximation converter types, the buffer must maintain a constant output voltage under dynamically changing load current conditions. In these types of converters, the comparison point is usually diode-clamped, but it may deviate several hundred millivolts resulting in high frequency modulation of the A/D input current. Open-loop and closed-loop buffers (also, op amps configured as followers) that exhibit high closed-loop output impedances and/or low unity gain crossover frequencies recover very slowly from output load current transients. This slow recovery leads to linearity errors or missing codes because of errors in the instantaneous input voltage. Therefore, the buffer (or op amp) chosen for this type of application should exhibit low output impedance and high unity gain bandwidth so that its output has had a chance to settle to its nominal value before the converter makes its comparison. The circuit in Figure 34 illustrates a settling measurement circuit for evaluating the recovery time of high speed buffers from an output load current transient. The input to the buffer is grounded for ease of measuring the recovery time, and two resistors are used to sum steady-state and transient load currents at the output. As a worst-case condition, R1, was chosen such that the BUF04 would source (or sink) a steady-state current of 25 mA. R2 was then chosen to add a 10 mA transient current upon the steady-state value. To set accurately the nodal voltages internal to the BUF04, the supply voltages were offset by the voltage applied to R1. Because of its high transimpedance, wide bandwidth, and low output impedance, the BUF04 exhibits an extremely fast recovery time of 60 ns to 0.01%, as shown in Figure 34. Results were identical regardless whether the BUF04 was sourcing or sinking current. V+ 10F t 59.00ns ISOURCE (4mA/DIV) 100 90 25mA 35mA VOUT (5mV/DIV) 0% 10 100mV 5mV 20ns Figure 35. BUF04's Output Load Current Recovery Time Terminated Line Drivers The BUF04's high output current, large slew rate, and wide bandwidth all combine to make it an ideal device for high speed line driver applications. As shown in Figure 36, the BUF04 can be configured for driving doubly terminated 50 and 75 cables. To optimize the circuit's pulse response, a capacitor, CT (CX + CTRIM), is connected across the series back termination. The BUF04 can drive a 50 line to 2.5 V and a 75 line to 3.75 V when operating on 15 V supplies. CT CX 6 RX 6' COAX RL RS, RL 50 75 RX 50 75 CX 91pF 62pF CT 3-15pF 3-15pF VIN RS ZO 50 75 3 BUF04 COAX RG-58 RG-59 Figure 36. Line Driver Configuration Low-Pass Active Filter 0.1F 7 3 BUF04 4 10F 6 0.1F TP1 R2 250 R1 200 VLOAD SOURCE: -5V SINK: +5V V- VIN SOURCE: 0 -2.5 V SINK: 0 +2.5V TP2 In many signal-conditioning applications, filters are required to band-limit noise or altogether eliminate other unwanted signals prior to conversion. Often, high frequency filters are needed for these applications; however, there are few op amps that exhibit the high open-loop gain and wide unity-gain crossover frequency required for these applications. As illustrated in Figure 37, the BUF04 and a handful of passive components can be configured as a high frequency, low-pass active filter. Since the filter configuration is a unity-gain Sallen-Key topology, the BUF04 is particularly well suited for this application. In this circuit, an additional resistor, R3, was added to prevent interaction between C2 and the BUF04's input capacitance. C1* 44pF (22pF x 2) Figure 34. Transient Output Load Current Test Circuit VIN R1 499 R2 499 C2* 22pF R3 47 3 6 BUF04 VOUT * SILVERED MICA OR DIPPED CERAMIC WO = 1 R1 * R2 * C1 * C2 ; Q= C1 4 * C2 Figure 37. A 10 MHz Low-Pass Active Filter REV. 0 -11- BUF04 Operation Within an Op Amp Feedback Loop Paralleling BUF04s for Increased Load Drive Capability The BUF04 is well suited as a current booster or isolation buffer within the closed loop of precision op amps such as the OP177, the OP97, the OP27, or the OP77. Since the BUF04 is a closed loop voltage buffer, no interstage coupling resistor between the op amp and the buffer's input is required for circuit stability. The wide bandwidth and high slew rate of the BUF04 assure that the loop has the characteristics of the op amp; hence, no additional rolloff is required. R1 100 2 VIN 3 OP177 6 3 BUF04 6 RL 500 GAIN 10 100 1000 R2 (k) 1 10 100 VOUT CL 1000pF R2 In applications where continuous output currents greater than 50 mA are required or where heat management is an issue, a number of BUF04s can be connected in parallel to reduce the drive requirement of any one buffer. An example of one such application is illustrated in Figure 39. In this circuit, the BUF04s are required to drive a doubly terminated 50 line to 5 V. This type of a load for a single BUF04 would certainly cause a power dissipation problem. Parallel operation results in lower input and output impedances and increased bias currents; on the other hand, input equivalent noise voltage is reduced and input offset voltage remains unchanged. R1 47 R3 100 3 BUF04 6 VIN 10V RS 50 R2 47 R4 100 5V RL 50 VOUT 3 BUF04 6 Figure 38. BUF04 as Booster Stage for a Precision Op Amp Figure 39. Paralleling BUF04s for High Output Currents Overdrive Recovery and Phase Reversal In applications where the inputs could be driven to the supply rails, the BUF04 recovers in 10 ns from positive or negative overdrive. The BUF04 does not exhibit any output voltage phase reversal when the input signal exceeds its input voltage range. -12- REV. 0 BUF04 * BUF04 SPICE Macro-model 7/93, Rev. A * JCB / PMI * * Copyright 1993 by Analog Devices, Inc. * * * Node assignments * noninverting input * positive supply * negative supply * output * * .SUBCKT BUF04 1 99 50 6 * * INPUT STAGE * R1 99 8 200 R2 10 50 200 V1 99 9 4.4 D1 9 8 DX V2 11 50 4.4 D2 10 11 DX I1 99 5 1.8E-3 I2 4 50 1.8E-3 Q1 50 3 5 QP Q2 99 3 4 QN Q3 8 61 30 QN Q4 10 7 30 QP R3 5 61 50E3 R4 4 7 50E3 CP1 61 99 14E-15 CP2 7 50 14E-15 RFB 6 2 100 * * INPUT ERROR SOURCES * IB1 99 1 0.7E-6 VOS 3 1 0.7E-6 LS1 30 2 1E-9 CS1 99 2 2.0E-12 CS2 99 1 3.0E-12 * EREF 97 0 22 0 1 * * TRANSCONDUCTANCE STAGE * R5 12 97 365E3 C3 12 97 8E-12 G1 97 12 99 8 SE-3 G2 12 97 10 50 SE-3 E3 13 97 POLY(1) 99 97 -2.5 1.1 E4 97 14 POLY(1) 97 50 -2.5 1.1 D3 12 13 DX D4 14 12 DX R6 12 15 200 C2 15 6 20E-12 * * POLE AT 200 MHz * R11 20 97 1E6 C7 20 97 0.759E-15 G7 97 20 12 22 1E-6 * * POLE AT 200 MHz * R12 21 97 1E6 C8 21 97 0.759E-15 G8 97 21 20 22 1E-6 * * OUTPU T STAGE * FSY 99 50 POLY(2) V7 V8 1.85E-3 1 1 R13 22 99 16.67E3 R14 22 50 16.67E3 R15 27 99 80 R16 27 50 80 L2 27 6 10E-9 G11 27 99 99 21 12.5E-3 G12 50 27 21 50 12.5E-3 V5 23 27 3.3 V6 27 24 3.3 D5 21 23 DX D6 24 21 DX G10 97 70 27 21 12.5E-3 D7 70 71 DX D8 72 70 DX V7 71 97 DC 0 V8 97 72 DC 0 * * MODELS USED * .MODEL QN NPN(BF= 1000 IS= 1E-15) .MODEL QP PNP(BF= 1000 IS= 1E-15) .MODEL DX D(IS= 1E-15) .ENDS BUF04 REV. 0 -13- BUF04 BUF04 SPICE 99 CP1 IB1 5 VOS Q2 3 4 R4 7 Q4 10 I2 D2 CP2 R2 11 V2 50 Q1 30 2 6 RFB I1 8 R3 61 LS1 CS2 Q3 V1 R1 9 D1 12 CS1 G1 97 G2 R5 C3 E3 12 D3 13 E4 D4 14 R6 C2 6 15 +IN 1 20 21 G7 R11 C7 G8 R12 C8 97 99 R13 FSY 70 22 G10 D7 71 V7 97 D8 72 V8 21 D6 24 G11 D5 23 V5 27 V6 R15 L2 6 R16 R14 G12 50 -14- REV. 0 BUF04 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 8 PIN 1 1 4 5 0.280 (7.11) 0.240 (6.10) 0.430 (10.92) 0.348 (8.84) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.100 (2.54) BSC 0.015 (0.381) TYP 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN SEATING PLANE 0.015 (0.381) 0.008 (0.204) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 8-Lead Cerdip (Q-8) 0.005 (0.13) MIN 0.055 (1.4) MAX 8-Lead Narrow-Body SO (R-8) 8 8 PIN 1 1 4 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 5 0.310 (7.87) 0.220 (5.59) 5 0.1574 (4.00) 0.1497 (3.80) PIN 1 1 4 0.2440 (6.20) 0.2284 (5.80) 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.100 0.070 (1.78) 0.014 (0.36) (2.54) 0.030 (0.76) BSC 0.1968 (5.00) 0.1890 (4.80) 0.0098 (0.25) 0.0040 (0.10) 0.102 (2.59) 0.094 (2.39) 0.0196 (0.50) x 45 0.0099 (0.25) 0.150 (3.81) MIN 0.015 (0.38) 0.008 (0.20) 15 0 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0098 (0.25) 0.0075 (0.19) 8 0 0.0500 (1.27) 0.0160 (0.41) SEATING PLANE REV. 0 -15- BUF04 -16- C1856-10-10/93 REV. 0 PRINTED IN U.S.A. |
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